This application is related to Korean Application No. 00-00670, filed Jan. 7, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to semiconductor devices and fabrication methods, and more particularly, to MOS-based semiconductor devices and substrates and methods of forming same.
Partially-depleted silicon-on-insulator (PDSOI) MOSFETs offer high speed and low power performance, but typically remain susceptible to parasitic floating body effects (FBE) which can seriously degrade device performance. Various techniques have been proposed for reducing FBE in SOI MOSFETs. One such technique includes using a narrow bandgap SiGe layer adjacent a source of an SOI NMOS field effect transistor. As will be understood by those skilled in the art, the use of a SiGe layer reduces the potential barrier for holes passing from the body region to the source region. Therefore, holes generated in the body region by impact ionization can more readily flow into the source region through the path of the pxe2x88x92Si(body)/n+SiGe(source)/n+Si(source). This and other related techniques are disclosed in articles by J. Sim et al. entitled xe2x80x9cElimination of Parasitic Bipolar-induced Breakdown Effects in Ultra-Thin SOI MOSFETs Using Narrow-Bandgap-Source (NBS) Structure,xe2x80x9d IEEE Trans. Elec. Dev., Vol. 42, No. 8, pp. 1495-1502, August (1995) and M. Yoshimi et al. entitled xe2x80x9cSuppression of the Floating-Body Effect in SOI MOSFETs by the Bandgap Engineering Method Using a Si1xe2x88x92xGex Source Structure,xe2x80x9d IEEE Trans. Elec. Dev., Vol. 44, No. 3, pp. 423-429, March (1997). U.S. Pat. No. 5,698,869 to Yoshimi et al. entitled xe2x80x9cInsulated-Gate Transistor Having Narrow-Bandgap-Sourcexe2x80x9d also discloses the use of a narrow bandgap material within a source region of a MOSFET.
Techniques to reduce FBE and improve channel characteristics in MOSFETs are also described in U.S. Pat. No. 5,891,769 to Liaw et al. entitled xe2x80x9cMethod for Forming a Semiconductor Device Having a Heteroepitaxial Layer.xe2x80x9d In particular, the ""769 patent discloses the use of a strained channel region to enhance carrier mobility within MOSFETs. This strained channel region may be formed by growing a silicon layer on an as-grown relaxed or unstrained SiGe layer. U.S. Pat. No. 5,963,817 to Chu et al. entitled xe2x80x9cBulk and Strained Silicon on Insulator Using Selective Oxidation,xe2x80x9d also discloses the use of SiGe layers, which selectively oxidize at faster rates relative to silicon, to improve FBE. Furthermore, U.S. Pat. Nos. 5,906,951 and 6,059,895 to Chu et al. disclose wafer bonding techniques and strained SiGe layers to provide SOI substrates. The use of wafer bonding techniques and SiGe layers to provide SOI substrates are also described in U.S. Pat. Nos. 5,218,213 and 5,240,876 to Gaul et al. Conventional techniques for forming SOI substrates are also illustrated by FIGS. 1A-1D and 2A-2D. In particular, FIG. 1A illustrates the formation of a handling substrate having a porous silicon layer therein and an epitaxial silicon layer thereon and FIG. 1B illustrates the bonding of a supporting substrate to a surface of the epitaxial silicon layer. The supporting substrate may include an oxide layer thereon which is bonded directly to the epitaxial silicon layer using conventional techniques. As illustrated by FIG. 1C, a portion of the handling substrate is then removed to expose the porous silicon layer. This removal step may be performed by grinding or etching away a portion of the handling substrate or splitting the porous silicon layer. As illustrated by FIG. 1D, a conventional planarization technique may then be performed to remove the porous silicon layer and provide an SOI substrate having a polished silicon layer thereon and a buried oxide layer therein. The conventional technique illustrated by FIGS. 1A-1D is commonly referred to as an epi-layer transfer (ELTRAN) technique. FIG. 2A illustrates a step of forming a handling substrate having a silicon layer thereon by implanting hydrogen ions into a surface of the substrate to define a buried hydrogen implant layer therein. Then, as illustrated by FIG. 2B, a supporting substrate is bonded to the handling substrate. A portion of the handling substrate is then removed by splitting the bonded substrate along the hydrogen implant layer, as illustrated by FIG. 2C. A conventional planarization technique may then be performed to remove the hydrogen implant layer, as illustrated by FIG. 2D. The conventional technique illustrated by FIGS. 2A-2D is commonly referred to as a xe2x80x9csmart-cutxe2x80x9d technique.
Unfortunately, although the use of strained silicon channel regions may enhance carrier mobility in both NMOS and PMOS devices, such strained regions typically degrade short channel device characteristics. Thus, notwithstanding the above-described techniques for forming MOSFETs and SOI substrates, there continues to be a need for improved methods of forming these structures that do not require the use of strained channel regions to obtain enhanced channel mobility characteristics, and structures formed thereby.
Embodiments of the present invention include semiconductor-on-insulator (SOI) substrates having buried Si1xe2x88x92xGex layers therein. A SOI substrate according to one embodiment of the present invention comprises a silicon wafer having an electrically insulating layer thereon and a Si1xe2x88x92xGex layer having a graded concentration of Ge therein extending on the electrically insulating layer. An unstrained silicon active layer is also provided in the SOI substrate. This unstrained silicon active layer extends on the Si1xe2x88x92xGex layer and forms a junction therewith. The unstrained silicon active layer also preferably extends to a surface of the SOI substrate, so that integrated circuit devices may be formed at the surface of the silicon active layer. To facilitate the use of relatively thin silicon active layers, the Si1xe2x88x92xGex layer is preferably epitaxially grown from the unstrained silicon active layer. This epitaxial growth step may include providing an unstrained silicon active layer (or initially epitaxially growing an unstrained silicon active layer on a substrate) and then continuing growth of a Si1xe2x88x92xGex layer on the active layer by increasing the concentration of Ge in a graded manner until a maximum desired Ge concentration is obtained. Further growth may then occur by reducing the concentration of Ge in a graded manner back to x=0. The grading of Ge in the Si1xe2x88x92xGex layer may constitute a linear grading.
The preferred SOI substrates may be fabricated by initially forming a handling substrate having an unstrained silicon layer therein and Si1xe2x88x92xGex layer extending on the silicon layer. A supporting substrate is then bonded to the handing substrate so that the Si1xe2x88x92xGex layer is disposed between the supporting substrate and the unstrained silicon layer. A portion of the handling substrate is then preferably removed from the supporting substrate to expose a surface of the silicon layer and define a semiconductor-on-insulator substrate having a buried Si1xe2x88x92xGex layer therein. Here, the buried Si1xe2x88x92xGex layer preferably has a graded concentration of Ge therein with a profile that decreases in a direction that extends from the supporting substrate to the surface of the silicon layer.
These methods may also include forming a handling substrate having an unstrained first silicon layer therein, a Si1xe2x88x92xGex layer extending on the first silicon layer and an unstrained or strained second silicon layer extending on the Si1xe2x88x92xGex layer. The bonding step may also be preceded by the step of thermally oxidizing the second silicon layer to define a thermal oxide layer on the Si1xe2x88x92xGex. The supporting substrate may also comprise an oxide surface layer thereon and the bonding step may comprise bonding the oxide surface layer to the thermal oxide layer. Alternatively, the bonding step may be preceded by the step of depositing an electrically insulating layer on the Si1xe2x88x92xGex layer and the bonding step may comprise bonding the oxide surface layer to the electrically insulating layer.
According to still another preferred method of forming a SOI substrate, the handling substrate may comprise a porous silicon layer therein and the removing step may comprise removing a portion of the handling substrate from the supporting substrate by splitting the porous silicon layer and then planarizing the porous silicon layer and the silicon layer in sequence. Preferred methods of forming handling substrates may also comprise epitaxially growing a Si1xe2x88x92xGex layer on a silicon layer and then implanting hydrogen ions through the Si1xe2x88x92xGex layer and the silicon layer to define a hydrogen implant layer in the handling substrate. The removing step may then be performed by splitting the hydrogen implant layer and then planarizing the hydrogen implant layer to expose a surface of the silicon layer. Semiconductor devices, including field effect transistors, may then be formed at this surface of the silicon layer.
An additional embodiment of the present invention includes semiconductor-on-insulator field effect transistors. Such transistors may comprise an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si1xe2x88x92xGex layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si1xe2x88x92xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. According to one aspect of this embodiment, the peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the Si1xe2x88x92xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si1xe2x88x92xGex layer varies from the peak level where 0.2 less than x less than 0.4 to a level where x=0 at the first junction.
The Si1xe2x88x92xGex layer may also define an interface with the underlying electrically insulating layer and the graded concentration of Ge in the Si1xe2x88x92xGex layer may increase from a level less than about x=0.1 at the interface with the electrically insulating layer to the peak level. The unstrained silicon active layer may also have a thickness of greater than about 600 xc3x85 and the Si1xe2x88x92xGex layer may have a thickness of less than about 800 xc3x85.
Higher drive current capability in PMOS transistors may also be achieved by reorganizing the dopant profiles in the channel region and in the body region. In particular, the different solubility of certain dopants in Si and Si1xe2x88x92xGex can be used advantageously to improve PMOS device characteristics. In a preferred PMOS transistor, the Si1xe2x88x92xGex layer is doped with an N-type dopant and the concentration of the N-type dopant in the Si1xe2x88x92xGex layer has a profile that decreases in the first direction towards the surface of the unstrained silicon active layer. This profile preferably has a peak level within the Si1xe2x88x92xGex layer and may decrease in the first direction and in a monotonic manner so that a continuously retrograded N-type dopant profile extends across the unstrained silicon active layer. This N-type dopant is preferably used to suppress punch-through in the body region, but may also be used to influence the threshold voltage of the PMOS transistor.
Additional semiconductor-on-insulator field effect transistors may also comprise an electrically insulating layer and a composite semiconductor active region on the electrically insulating layer. This composite semiconductor active region comprises a silicon active layer having a thickness greater than about 600 xc3x85 and a single Si1xe2x88x92xGex layer disposed between the electrically insulating layer and the silicon active layer. The Si1xe2x88x92xGex layer forms a first junction with the silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards a surface of the silicon active layer. An insulated gate electrode is also provided on the surface. The peak level of Ge in the Si1xe2x88x92xGex layer is preferably greater than x=0.15 and the concentration of Ge in the Si1xe2x88x92xGex layer varies from the peak level to a level less than about x=0.1 at the first junction. More preferably, the concentration of Ge in the Si1xe2x88x92xGex layer varies from the peak level where 0.2 less than x less than 0.4 to a level where x=0 at the first junction. The Si1xe2x88x92xGex layer may also define an interface with the electrically insulating layer and the graded concentration of Ge in the Si1xe2x88x92xGex layer also increases from a level less than about x=0.1 at the interface to the peak level.
A further embodiment of the present invention comprises a PMOS field effect transistor having a composite semiconductor active region therein that extends on an electrically insulating layer. This composite semiconductor active region comprises a single Si1xe2x88x92xGex layer having a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level within the single Si1xe2x88x92xGex layer towards a surface thereof. An unstrained silicon active layer is also provided that extends from a first junction with the single Si1xe2x88x92xGex layer to the surface. The composite semiconductor active region also has an at least substantially retrograded N-type dopant profile therein that extends to the surface and has a peak level in the single Si1xe2x88x92xGex layer. The total charge provided by this N-type dopant influences the threshold voltage of the PMOS transistor. The N-type dopant in the single Si1xe2x88x92xGex layer also significantly inhibits punch-through caused by depletion layers that may extend between the source and drain regions. Lightly doped P-type source and drain regions are also preferably provided. These regions extend in the silicon active layer and opposite the insulated gate electrode. A source-side pocket implant region of N-type conductivity is also provided and this pocket implant region extends between the lightly doped P-type source region and the single Si1xe2x88x92xGex layer. This pocket implant region forms rectifying and os with the source region and the single Si1xe2x88x92xGex layer, respectively, and operates to suppress junction leakage.
A still further embodiment of a semiconductor-on-insulator field effect transistor comprises a bulk silicon region and an electrically insulating layer on the bulk silicon region. An unstrained silicon active layer having a first thickness is also provided on the electrically insulating layer and an insulated gate electrode with sidewall insulating spacers is formed on a surface of the unstrained silicon active layer. A Si1xe2x88x92xGex layer of first conductivity type is disposed between the electrically insulating layer and the unstrained silicon active layer. In particular, the Si1xe2x88x92xGex layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface. Lightly doped source and drain regions of second conductivity type are also provided. These lightly doped regions extend in the unstrained silicon active layer, but to a depth less than the thickness of the unstrained silicon active layer. In addition, a source-side pocket implant region of first conductivity type is provided in the unstrained silicon active layer, and this source-side pocket implant region extends between the lightly doped source region and the Si1xe2x88x92xGex layer. According to a preferred aspect of this embodiment, the Si1xe2x88x92xGex layer has a retrograded first conductivity type doping profile therein relative to the surface. This retrograded first conductivity type doping profile may be a retrograded arsenic (or arsenic/phosphorus) doping profile and may result in the Si1xe2x88x92xGex layer having a greater concentration of first conductivity type dopants therein relative to the maximum concentration of first conductivity type dopants in a channel region within the unstrained silicon active layer. In particular, the retrograded dopant profile has a peak in the Si1xe2x88x92xGex layer and a minimum underneath the gate electrode. This retrograded profile preferably decreases monotonically from the peak level to the minimum level, however, other retrograded profiles may also be achieved. The thickness of the unstrained silicon active layer and the total amount of dopants in the channel region and underlying Si1xe2x88x92xGex layer can also be carefully controlled to achieve a desired threshold voltage and inhibit punch-through.
Embodiments of the present invention also include methods of forming field effect transistors by forming an insulated gate electrode on a surface of a semiconductor-on-insulator substrate. This substrate includes an electrically insulating layer, an unstrained silicon active layer on the electrically insulating layer and a Si1xe2x88x92xGex epitaxial layer having a graded concentration of Ge therein disposed between the electrically insulating layer and the unstrained silicon active layer. Steps are also performed to form source and drain regions of first conductivity type in the unstrained silicon active layer and also form source-side and drain-side pocket implant regions of second conductivity type that extend in the unstrained silicon active layer and in the Si1xe2x88x92xGex epitaxial layer. These pocket implant regions form respective P-N junctions with the source and drain regions. The step of forming an insulated gate electrode is preferably preceded by the step of implanting threshold voltage control dopants of first conductivity type into the unstrained silicon active layer. These threshold voltage control dopants may then be annealed and redistributed as a result of different dopant solubility in Si and Si1xe2x88x92xGex after the insulated gate electrode has been formed, to establish a retrograded profile of threshold voltage control dopants in the Si1xe2x88x92xGex epitaxial layer and silicon active layer. The dopants in the Si1xe2x88x92xGex epitaxial layer also inhibit punch-through in PMOS devices and reduce floating body effects in NMOS devices.
The substrates and forming methods of the present invention can be utilized to form NMOS transistors having reduced floating body effects (FBE). The reduction in FBE occurs because the buried SiGe layer, having a graded Ge concentration therein, reduces the potential barrier for holes passing from the body region to the source region. Therefore, holes generated in the body region by impact ionization can more readily flow into the source region through the path of the pxe2x88x92Si(body)/pxe2x88x92SiGe(body)/n+SiGe(source)/n+Si(source). NMOS transistors having well controlled kink effect characteristics and Id v. Vg curves having evenly distributed subthreshold slope with respect to Vds can also be formed. The substrates and forming methods of the present invention can also be utilized to provide PMOS transistors having excellent drive capability resulting from higher inversion-layer carrier mobility in the channel regions. This improved drive capability is achieved by reorganizing the channel region dopants through annealing so that a retrograded dopant profile and a desired threshold voltage are simultaneously achieved. This reorganization of the channel region dopants can also be used to enhance pocket ion implantation efficiency. The threshold voltage roll-off characteristics of these NMOS and PMOS devices can also demonstrate reduced short channel effects (RSCE), and the suppressed parasitic bipolar action (PBA) in the devices can be used to reduce off-leakage current.